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preliminary rev. 0.5 9/12 copyright ? 2012 by silicon laboratories si87xx this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si87xx 5 k v led e mulator i nput , o pen c ollector o utput i solators features applications safety regulatory approvals (pending) description the si87xx isolators are pin-compatible, one-channel, drop-in replacements for popular optocouplers with data rates up to 15 mbps. these devices isolate high-speed di gital signals and offer performance, reliability, and flexibility advantag es not available with optocoupler solutions. the si87xx series is based on silicon labs' proprietary cmos isolation technology for low-power and high-speed operation and are resistant to the wear-out effects found in optocouplers that degrade performance with increasing temperature, forward current, and device age. as a result, the si87xx series offer longer service life and dramatically higher reliability compared to optocouplers. ordering options include open collector output with an d without integrated pull-up resistor and output enable options. ? pin-compatible, drop-in upgrades for popular high-speed digital optocouplers ? performance and reliability advantages vs. optocouplers ?? resistant to temperature, age and forward current effects ?? 10x lower fit rate for longer service life ?? higher common-mode transient immunity: >50 kv/s typical ?? lower power and forward input diode current ? pcb footprint compatible with optocoupler packaging ? wide range of product options ? 1 channel diode emulator input ? 3 to 30 v open collector output ? propagation delay 30 ns ? data rates dc to 15 mbps ? 3.75 and 5 kv reinforced isolation ?? ul, csa, vde ? wide operating temperature range ?? ?40 to +125 c ? rohs-compliant packages ?? soic-8 ?? dip8 ?? sdip6 ?? lga8 ? industrial automation ? motor controls and drives ? isolated switch mode power supplies ? isolated data acquisition ? test and measurement equipment ? ul 1577 recognized ?? up to 5000 vrms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ?? iec 60747-5-2 (vde 0884 part 2) (reinforced insulation) ? cqc certification approval ?? gb4943.1 patent pending pin assignments: see page 18 soic-8, dip8, lga8 open collector output sdip6 open collector output soic-8, dip8, lga8 open collector output with 20 k ? pull-up resistor soic-8, dip8, lga8 open collector output with output enable
si87xx 2 preliminary rev. 0.5 functional block diagram diode emulator i f a1 output stage (open-collector) out vdd xmit gnd rec c1
si87xx preliminary rev. 0.5 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. technical descript ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1. device behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1. input circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2. output circuit design and powe r supply connections . . . . . . . . . . . . . . . . . . . . . . . 15 5. pin descriptions (soic-8, dip8, lga8) open collector . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. pin descriptions (soic-8, dip8, lga8) output enable . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. pin descriptions (sdip6) open collect or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. pin descriptions (soi c-8, dip8, lga8) 20 k ? pull-up resistor . . . . . . . . . . . . . . . . . . 19 9. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. package outline: 8-pin narr ow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. package outline: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13. land pattern: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14. package outline: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 15. land pattern: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 16. package outline: lga8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 17. land pattern: lga8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 18. top marking: 8-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 19. top marking: dip8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 20. top marking: sdip6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 21. top marking: lga8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
si87xx 4 preliminary rev. 0.5 1. electrical specifications table 1. recommended operating conditions parameter symbol min typ max unit v dd supply voltage (open collector output) v dd 3?30v input current si87xxa devices si87xxb devices si87xxc devices i f(on) 3 6 3 ? ? ? 15 30 15 ma ma ma operating temperature (ambient) t a ?40 ? 125 c table 2. electrical characteristics v dd = 5 v; gnd = 0 v; t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit dc parameters supply voltage v dd open collector output 3 ? 30 v supply current i dd output high or low (v dd = 5 to 30 v) ? ? 1.7 ma input current threshold i f(th) si87xxa devices si87xxb devices si87xxc devices 3 6 3 ? ? ? ? ? ? ma ma ma input current rising edge hysteresis i hys si87xxa devices si87xxb devices si87xxc devices ? ? ? 0.17 0.34 0.17 ? ? ? ma ma ma input forward voltage (off) v f(off) measured at anode with respect to cathode. ?? 1v input forward voltage (on) v f(on) measured at anode with respect to cathode. 1.7 ? 2.8 v input reverse breakdown voltage bvr ensures that reverse current is lim- ited to a safe level. ?0.3 ? ? v input capacitance c i f=100khz, v f =0v, v f =2v ? ? 15 15 ? ? pf pf logic low output voltage v ol i ol =3ma, v dd = 3.3 or 5 v i ol =13ma, v dd =5.5v ? ? ? ? 0.4 0.7 v v logic high output current i oh v dd =v out =5.5v v dd =v out =24v ? ? ? ? 0.5 1 a a peak output current i opk peak dc collector current drive (v dd =5v) ?50?ma output low impedance r ol ??54 ? pull-up resistor r pu using internal pull-up ? 20 ? k ? enable high min v eh 2?30v enable low max v el ??0.8v enable high current draw i eh v dd =v eh =5v ? 20 ? a enable low current draw i el v dd =5v, v el = 0 v ? ?10 0 a
si87xx preliminary rev. 0.5 5 ac switching parameters (v dd =5v, r l =350 ? , c l = 15 pf) maximum data rate f data si87xxa devices si87xxb devices si87xxc devices dc dc dc ? ? ? 15 15 1 m bps m bps m bps minimum pulse width mpw si87xxa devices si87xxb devices si87xxc devices 66 66 1 ? ? ? ? ? ? ns ns s propagation delay (low-to-high) t plh c l = 15 pf using 350 ? pull-up ? ? 60 ns propagation delay (high-to-low) t phl c l = 15 pf using 350 ? pull-up ? ? 60 ns pulse width distortion pwd | t plh ? t phl |? ? 2 0 n s propagation delay skew t psk(p-p) t psk(p-p) is the magnitude of the dif- ference in prop delays between dif- ferent units operating at same supply voltage, load, and ambient temp. ??20ns rise time t r c l = 15 pf using 350 ? pull-up ? 15 ? ns fall time t f c l = 15 pf using 350 ? pull-up ? 5 ? ns device startup time t start ??40s common mode transient immunity cmti output = low or high i f = 3 ma for si87xxa devices i f = 6 ma for si87xxb devices i f = 3 ma for si87xxc devices 20 35 20 35 50 35 ? ? ? kv/s kv/s kv/s table 2. electrical characteristics (continued) v dd = 5 v; gnd = 0 v; t a = ?40 to +125 c; typical specs at 25 c parameter symbol test condition min typ max unit
si87xx 6 preliminary rev. 0.5 table 3. regulatory information (pending)* csa the si87xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 1000 v rms reinforced insulation work ing voltage; up to 1000 v rms basic insulation working voltage. 60601-1: up to 250 v rms reinforced insulation working voltage; up to 500 v rms basic insulation working voltage. vde the si87xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1414 v peak for reinforced insulation working voltage. ul the si87xx is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si87xx is certified under gb4943.1-2011. for more details, see file number pending. rated up to 1000 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. *note: regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "9.ordering guide" on page 20. table 4. insulation and safety-related specifications parameter symbol test condition value unit soic-8 dip8 sdip6 lga8 nominal air gap (clearance) l(io1) 4.9 min 7.4 min 8.0 min 9.6 min mm nominal external tracking (creepage) l(io2) 4.8 min 8.0 min 8.0 min 10.0 min mm minimum internal gap (internal clearance) 0.016 0.016 0.016 0.016 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 600 v erosion depth ed 0.031 0.031 pending 0.021 mm resistance (input-output)* r io 10 12 10 12 10 12 10 12 ? capacitance (input-output)* c io f=1mhz1111pf *note: to determine resistance and capacitance, the si87xx is converted into a 2-terminal device. pins 1?4 (1?3, sdip6) are shorted together to form the firs t terminal, and pins 5?8 (4?6, sdip6) are shorted together to form the second terminal. the parameters are then measured between these two terminals.
si87xx preliminary rev. 0.5 7 table 5. iec 60664-1 (vde 0844 part 2) ratings parameter test condition specification soic-8 dip8 sdip6 lga8 basic isolation group material group i i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iv i-iv i-iv rated mains voltages < 450 v rms i-iii i-iii i-iv i-iv rated mains voltages < 600 v rms i-iii i-iii i-iv i-iv rated mains voltages < 1000 v rms ? ? ? i-iii table 6. iec 60747-5-2 insulation characteristics* parameter symbol test condition characteristic unit soic-8 dip8 sdip6 lga8 maximum working insulation voltage v iorm 630 891 1140 1414 v peak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 1181 1671 2138 2652 v peak transient overvoltage v iotm t = 60 sec 6000 6000 8000 8000 v peak pollution degree (din vde 0110, table 1) 2222 insulation resistance at t s , v io =500v r s >10 9 >10 9 >10 9 >10 9 ? *note: this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the si87 xx provides a climate classification of 40/125/21.
si87xx 8 preliminary rev. 0.5 figure 1. (soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 7. iec safety limiting values parameter symbol test condition max unit soic-8 dip8 sdip6 lga8 case temperature t s 140 140 140 140 c input current i s ? ja = 110 c/w (soic-8), 110 c/w (dip8), 105 c/w (sdip6), 220 c (lga8), v f =2.8v, t j =140c, t a =25c 370 370 390 185 ma output power p s 1110.5w note: maximum value allowed in the event of a failure; also see the thermal derating curve in figures 1, 2, 3, and 4. table 8. thermal characteristics parameter symbol typ unit soic-8 dip8 sdip6 lga8 ic junction-to-air thermal resistance ? ja 110 110 105 220 oc/w 400 600 800 1000 1200 ower ps,inputcurrent is ps(mw) is(ma) 0 200 0 20406080100120140 outputpo ts casetemperature(c)
si87xx preliminary rev. 0.5 9 figure 2. (dip8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 3. (sdip6) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 400 600 800 1000 1200 ower ps,inputcurrent is ps(mw) is(ma) 0 200 0 20406080100120140 outputpo ts casetemperature(c) 400 600 800 1000 1200 ower ps,inputcurrent is ps(mw) is(m a) 0 200 0 20406080100120140 outputpo ts casetemperature(c)
si87xx 10 preliminary rev. 0.5 figure 4. (lga8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 200 300 400 500 600 o wer ps,inputcurrent is ps(mw) is(ma) 0 100 0 20406080100120140 outputp o ts casetemperature(c)
si87xx preliminary rev. 0.5 11 table 9. absolute maximum ratings* parameter symbol min max unit storage temperature t stg ?65 +150 c operating temperature t a ?40 +125 c junction temperature t j ?+140c average forward input current si87xxa devices si87xxb devices si87xxc devices i f(avg) ? ? ? 15 30 15 ma ma ma peak transient input current (< 1 s pulse width, 300 ps) i ftr ?1 a reverse input voltage v r ?0.3 v supply voltage v dd ?0.5 36 v output voltage v out ?0.5 36 v enable voltage v out ?0.5 v dd +0.5 v output sink current i sink ?15ma average output current i o(avg) ?8ma peak output current (v dd =5v) i opk ?75ma input power dissipation p i ?90mw output power dissipation p o ?50mw total power dissipation p t ?140mw lead solder temperature (10 s) ? 260 c hbm rating esd 3 ? kv machine model esd 200 ? v cdm 500 ? v maximum isolation voltage (1 s) soic-8 ? 4500 v rms maximum isolation voltage (1 s) dip8 ? 4500 v rms maximum isolation voltage (1 s) sdip6 ? 6500 v rms maximum isolation voltage (1 s) lga8 ? 6500 v rms *note: permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions specified in the operational sections of this data sheet.
si87xx 12 preliminary rev. 0.5 2. application information 2.1. theory of operation the si87xx are pin-compatible, one-channel, drop-in replacements for popular optocouplers with data rates up to 15 mbps. the operation of an si87xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple architecture provid es a robust isolated data path and requires no special considerations or initializ ation at start-up. a simplified block diagr am for the si87xx is shown in figure 5. figure 5. simplified channel diagram rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver led emulator output stage open collector
si87xx preliminary rev. 0.5 13 3. technical description 3.1. device behavior truth tables for the si87xx are summarized in table 10. 3.2. device startup output v o is held low during power-up until v dd rises above the uvlo+ threshold for a minimum time period of t start . following this, the output is high when the current flowing from anode to cathode is > i f(on) . device startup, normal operation, and shutdown behavior is shown in figure 6. figure 6. si87xx operating behavior (i f > i f(min) when v f > v f(min) ) table 10. si87xx truth table summary 1 input v dd en 2 v o 3 off > uvlo h high off > uvlo l high off < uvlo h high off < uvlo l high on > uvlo h low on > uvlo l high on < uvlo h high on < uvlo l high notes: 1. this truth table assumes v dd is powered. uvlo is typically 2.8 v. 2. si8712 only. 3. the output voltage level is determined by the external pull-up supply. i f v o v dd t start t plh t phl i f(on) i hys uvlo voltage level determined by external pull-up supply t uvlo t uvlo t plh
si87xx 14 preliminary rev. 0.5 4. applications the following sections detail the input and output circuits necessary for proper operation of the si87xx family. 4.1. input circuit design opto coupler manufacturers typically recommend the circuits show n in figures 7 and 8. these circuits are specifically designed to improve op to-coupler input common-mode rejection and increase noise immunity. figure 7. si87xx input circuit figure 8. high cmr si87xx input circuit the optically-coupled circuit of figu re 7 turns the led on when the contro l input is high. however, internal capacitive coupling from the led to the power and ground conductors can momentarily force the led into its off state when the anode and cathode inputs are subjected to a high common-mode transient. the circuit shown in figure 8 addresses this issue by using a value of r1 suff iciently low to overdrive th e led, ensuring it remains on during an input common-mode transient. q1 shorts the led off in the low output state, again increasing common- mode transient immunity. some opto coupler applications recommend reverse-biasing the led when the control input is off to prevent coupled noise from energizing the led. the si87xx input circuit requires less current and has twice the off-state noise margin compared to opto couplers. however, high cmr opto coupler designs that overdrive the led (see figure 8) may require increasing the value of r1 to limit input current i f to its maximum rating when using the si87xx. in addition, there is no benefit in driving the si 87xx input diode into reverse bias when in the off state. consequently, opto coupler circuits usi ng this technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e.g., add a clamp diode or curren t limiting resistor) to ensure that the anode pin of the si87xx is no more than ?0.3 v with respect to the cathode when reverse-biased. r1 1 2 3 4 si87xx vdd open drain or collector control input anode cathode n/c n/c r1 1 2 3 4 si87xx vdd control input anode cathode n/c n/c q1
si87xx preliminary rev. 0.5 15 new designs should consider the input circuit configurat ions of figure 9, which are more efficient than those of figures 7 and 8. as shown, s1 and s2 represent any suitable switch, such as a bjt or mosfet, analog transmission gate, processor i/o, etc. also, note that th e si87xx input can be driven from the i/o port of any mcu or fpga capable of sourcing a minimum of 6 ma (see figu re 9b). additionally, note that the si87xx propagation delay and output drive do not significantly change for values of i f between i f(min) and i f(max) . figure 9. si87xx other input circuit configurations 4.2. output circuit desi gn and power supply connections the speed of the open collector circuit is depende nt upon the supply, vcc, the pullup resistor, r l , and the load modeled by c l . figure 10 illustrates th ree common circui t output configurations. for v dd = 5 v operation, r l >350 ?? is recommended to ensure proper v ol levels. for v dd = 30 v operation, r l > 2.1 k ?? is recommended to ensure proper v ol levels. if the enable pin is used (see figure 10b) and two separate supplies power v dd and the v o pullup resistor, the enable pin should be referenced to the v dd pin because v o cannot exceed v dd by more than 0.5 v. figure 10c illustrates a circuit using the internal 20 k ? resistor. note that gnd can be biased at, above, or below ground as long as the voltage on v dd with respect to gnd is a maximum of 30 v. v dd decoupling capacitors should be placed as cl ose to the package pins as possible. the optimum values for these capacitors depend on load cu rrent and the distance between the chip and its power source. it is recommended that 0.1 and 1 f bypass ca pacitors be used to reduce high-frequency noise and maximize performance. opto replacem ent applications should limit their supply voltages to 30 v or less. figure 10. si87xx output circuit configurations si87xx 1 2 3 4 +5v control input s1 n/c anode cathode n/c si87xx a b r1 s2 4 n/c 3 cathode 2 mcu i/o port pin anode r1 1 n/c si87xx si87xx b 5 gnd 6 vo 7 ve 8 vdd 0.1, 1 f en vcc1 3-30 v r l c l vcc2 3-30 v c 5 gnd 6 vo 7 8 r l c l 0.1, 1 f vcc 3-30 v vl vdd si87xx a 5 gnd 6 vo 7 ve 8 vdd r l c l 0.1, 1 f en vcc 3-30 v
si87xx 16 preliminary rev. 0.5 5. pin descriptions (soic- 8, dip8, lga8) open collector figure 11. pin configuration table 11. pin descriptions (soic-8, dip8, lga8) open collector pin name description 1 nc no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc no connect. 5 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. 7 nc no connect. 8v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane.
si87xx preliminary rev. 0.5 17 6. pin descriptions (soic-8, dip8, lga8) output enable figure 12. pin configuration table 12. pin descriptions (soic-8, dip8, lga8) output enable pin name description 1 nc no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc no connect. 5 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. 7v e output enable. 8v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane.
si87xx 18 preliminary rev. 0.5 7. pin descriptions (sdip6) open collector figure 13. pin configuration table 13. pin descriptions (sdip6) open collector pin name description 1 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 2 nc no connect. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 5v o output signal. 6v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane.
si87xx preliminary rev. 0.5 19 8. pin descriptions (soic-8, dip8, lga8) 20 k ? pull-up resistor figure 14. pin configuration table 14. pin descriptions (soic-8, dip8, lga8) 20 k ? pull-up resistor pin name description 1 nc no connect. 2 anode anode of led emulator. v o follows the signal applied to this input with respect to the cathode input. 3 cathode cathode of led emulator. v o follows the signal applied to an ode with respect to this input. 4 nc no connect. 5 gnd external mosfet source connection and ground reference for v dd . this terminal is typically connected to ground but may be tied to a negative or positive voltage. 6v o output signal. 7v l output pull-up load 8v dd output-side power supply input referenced to gnd (30 v max). *note: no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane.
si87xx 20 preliminary rev. 0.5 9. ordering guide table 15. si87xx ordering guide* new ordering part number (opn) ordering options input/output configuration data rate (cross reference) insulation rating temp range pkg type open collector output (available in soic-8, dip8, and sdip6) si8710ac-b-is (in production) led input open collector output 15 mbps acpl-w611, ps9303l2 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8710bc-b-is (in production) high cmti led input open collector output 15 mbps acpl-w611, ps9303l2 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8710cc-b-is (in production) led input open collector output 1mbps acpl-w611, ps9303l2 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8710ac-b-ip (in production) led input open collector output 15 mbps hcpl-4502 3.75 kvrms ?40 to +125 c dip8/gw si8710bc-b-ip (in production) high cmti led input open collector output 15 mbps hcpl-4502 3.75 kvrms ?40 to +125 c dip8/gw si8710cc-b-ip (in production) led input open collector output 1mbps hcpl-4502 3.75 kvrms ?40 to +125 c dip8/gw si8710ad-b-is (sampling) led input open collector output 15 mbps acpl-w611, ps9303l2 5.0 kvrms ?40 to +125 c sdip6 si8710bd-b-is (sampling) high cmti led input open collector output 15 mbps acpl-w611, ps9303l2 5.0 kvrms ?40 to +125 c sdip6 si8710cd-b-is (sampling) led input open collector output 1mbps acpl-w611, ps9303l2 5.0 kvrms ?40 to +125 c sdip6 *note: all packages are rohs-compliant. moisture sensitivity leve l is msl3 with peak reflow te mperature of 260 c according to the jedec industry standard classifications and peak solder temperature.
si87xx preliminary rev. 0.5 21 open collector output with 20 k ? pullup resistor (available in soic-8, dip8, and lga8) si8711ac-b-is (in production) led input open collector output with integrated pullup 15 mbps hcpl-4506 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8711bc-b-is (in production) high cmti led input open collector output with integrated pullup 15 mbps hcpl-4506 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8711cc-b-is (in production) led input open collector output with integrated pullup 1mbps hcpl-4506 (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8711ac-b-ip (in production) led input open collector output with integrated pullup 15 mbps hcpl-4506 3.75 kvrms ?40 to +125 c dip8/gw si8711bc-b-ip (in production) high cmti led input open collector output with integrated pullup 15 mbps hcpl-4506 3.75 kvrms ?40 to +125 c dip8/gw si8711cc-b-ip (in production) led input open collector output with integrated pullup 1mbps hcpl-4506 3.75 kvrms ?40 to +125 c dip8/gw si8711ad-b-im (sampling) led input open collector output with integrated pullup 15 mbps hcnw-4506 5.0 kvrms ?40 to +125 c lga8 SI8711BD-B-IM (sampling) high cmti led input open collector output with integrated pullup 15 mbps hcnw-4506 5.0 kvrms ?40 to +125 c lga8 si8711cd-b-im (sampling) led input open collector output with integrated pullup 1mbps hcnw-4506 5.0 kvrms ?40 to +125 c lga8 table 15. si87xx ordering guide* (continued) new ordering part number (opn) ordering options input/output configuration data rate (cross reference) insulation rating temp range pkg type *note: all packages are rohs-compliant. moisture sensitivity leve l is msl3 with peak reflow te mperature of 260 c according to the jedec industry standard classifications and peak solder temperature.
si87xx 22 preliminary rev. 0.5 open collector output with output enable (available in soic-8, dip8, and lga8) si8712ac-b-is (in production) led input open collector output with enable 15 mbps hcpl-261x/260x (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8712bc-b-is (in production) high cmti led input open collector output with enable 15 mbps hcpl-261x/260x (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8712cc-b-is (in production) led input open collector output with enable 1mbps hcpl-261x/260x (functional match) 3.75 kvrms ?40 to +125 c soic-8 si8712ac-b-ip (in production) led input open collector output with enable 15 mbps hcpl-261x/260x 3.75 kvrms ?40 to +125 c dip8/gw si8712bc-b-ip (in production) high cmti led input open collector output with enable 15 mbps hcpl-261x/260x 3.75 kvrms ?40 to +125 c dip8/gw si8712cc-b-ip (in production) led input open collector output with enable 1mbps hcpl-261x/260x 3.75 kvrms ?40 to +125 c dip8/gw si8712ad-b-im (sampling) led input open collector output with enable 15 mbps hcnw-2611 5.0 kvrms ?40 to +125 c lga8 si8712bd-b-im (sampling) high cmti led input open collector output with enable 15 mbps hcnw-2611 5.0 kvrms ?40 to +125 c lga8 si8712cd-b-im (sampling) led input open collector output with enable 1mbps hcnw-2611 5.0 kvrms ?40 to +125 c lga8 table 15. si87xx ordering guide* (continued) new ordering part number (opn) ordering options input/output configuration data rate (cross reference) insulation rating temp range pkg type *note: all packages are rohs-compliant. moisture sensitivity leve l is msl3 with peak reflow te mperature of 260 c according to the jedec industry standard classifications and peak solder temperature.
si87xx preliminary rev. 0.5 23 10. package outline: 8-pin narrow body soic figure 15 illustrates the package details for the si87xx in an 8-pin narrow-b ody soic package. table 16 lists the values for the di mensions shown in the illustration. figure 15. 8-pin narrow body soic package table 16. 8-pin narrow body soic package diagram dimensions symbol millimeters min max a1 . 3 51 . 7 5 a1 0.10 0.25 a2 1.40 ref 1.55 ref b0 . 3 30 . 5 1 c0 . 1 90 . 2 5 d4 . 8 05 . 0 0 e3 . 8 04 . 0 0 e 1.27 bsc h5 . 8 06 . 2 0 h0 . 2 50 . 5 0 l0 . 4 01 . 2 7 ? 0 ? 8 ? ?
si87xx 24 preliminary rev. 0.5 11. land pattern: 8-pin narrow body soic figure 16 illustrates the recommended land pattern details for the si87xx in an 8-pin narrow-body soic. table 17 lists the values for the dimens ions shown in the illustration. figure 16. 8-pin narrow body soic land pattern table 17. 8-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si87xx preliminary rev. 0.5 25 12. package outline: dip8 figure 17 illustrates the package details for the si87xx in a dip8 package. table 18 lists the values for the dimensions shown in the illustration. figure 17. dip8 package table 18. dip8 package diagram dimensions dimension min max a ? 4.19 a1 0.55 0.75 a2 3.17 3.43 b 0.35 0.55 b2 1.14 1.78 b3 0.76 1.14 c 0.20 0.33 d 9.40 9.90 e 7.37 7.87 e1 6.10 6.60 e2 9.40 9.90 e 2.54 bsc. l 0.38 0.89 aaa ? 0.25 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si87xx 26 preliminary rev. 0.5 13. land pattern: dip8 figure 18 illustrates the reco mmended land pattern details for the si87xx in a dip8 package. table 19 lists the values for the di mensions shown in the illustration. figure 18. dip8 land pattern table 19. dip8 land pattern dimensions* dimension min max c8 . 8 58 . 9 0 e2 . 5 4 b s c x0 . 6 00 . 6 5 y1 . 6 51 . 7 0 *note: this land pattern design is ba sed on the ipc-7351 specification. ?
si87xx preliminary rev. 0.5 27 14. package outline: sdip6 figure 19 illustrates the package details for the si87xx in an sdip 6 package. table 20 lists the values for the dimensions shown in the illustration. figure 19. sdip6 package table 20. sdip6 package diagram dimensions dimension min max a?2 . 6 5 a1 0.10 0.30 a2 2.05 ? b0 . 3 10 . 5 1 c0 . 2 00 . 3 3 d 4.58 bsc e 11.50 bsc e1 7.50 bsc e 1.27 bsc l0 . 4 01 . 2 7 h0 . 2 50 . 7 5 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si87xx 28 preliminary rev. 0.5 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 table 20. sdip6 package diagram dimensions (continued) dimension min max notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si87xx preliminary rev. 0.5 29 15. land pattern: sdip6 figure 20 illustrates the recommended land pattern details for the si87xx in an sdip6 package. table 21 lists the values for the di mensions shown in the illustration. figure 20. sdip6 land pattern table 21. sdip6 land pattern dimensions* dimension min max c 10.45 10.50 e1 . 2 7 b s c x0 . 5 50 . 6 0 y2 . 0 02 . 0 5 *note: this land pattern design is ba sed on the ipc-7351 specification. ?
si87xx 30 preliminary rev. 0.5 16. package outline: lga8 figure 21 illustrates the package deta ils for the si87xx in an lga8 package . table 22 lists the values for the dimensions shown in the illustration. figure 21. lga8 package table 22. package diagram dimensions dimension min nom max a 0.74 0.84 0.94 b 1.15 1.20 1.25 d 10.00 bsc. e 2.54 bsc. e 12.50 bsc. l 1.05 1.10 1.15 l1 0.05 0.10 0.15 aaa ? ? 0.10 bbb ? ? 0.10 ccc ? ? 0.10 ddd ? ? 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si87xx preliminary rev. 0.5 31 17. land pattern: lga8 figure 22 illustrates the recommended l and pattern details for t he si87xx in an lga8 package. table 23 lists the values for the di mensions shown in the illustration. figure 22. lga8 land pattern table 23. lga8 land pattern dimensions dimension feature (mm) c1 pad column spacing 11.80 e pad row pitch 2.54 x1 pad width 1.30 y1 pad length 1.80 notes: 1. this land pattern design is based on ipc-7351 specifications. 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. ?
si87xx 32 preliminary rev. 0.5 18. top marking: 8-p in narrow body soic figure 23. 8-pin narrow body soic top marking table 24. 8-pin narrow body soic top marking explanation line 1 marking: customer part number si87xxxx line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 43 mils diameter left-justified ?e4? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date.
si87xx preliminary rev. 0.5 33 19. top marking: dip8 figure 24. dip8 top marking table 25. dip8 top marking explanations line 1 marking: customer part number si87xxxx line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 51 mils diameter center-justified ?e4? pb-free symbol country of origin (iso-code abbreviation) th ?
si87xx 34 preliminary rev. 0.5 20. top marking: sdip6 figure 25. sdip6 top marking table 26. sdip6 top marking explanations line 1 marking: device 87xxxx line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. line 4 marking: country of origin (iso-code abbreviation) th ?
si87xx preliminary rev. 0.5 35 21. top marking: lga8 figure 26. lga8 top marking table 27. lga8 top marking explanations line 1 marking: device part number si87xxxx line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly release. rttttt = mfg code manufacturing code from the assembly purchase order form. ?r? indicates revision. line 3 marking: circle = 1.6 mm diameter center-justified "e4" pb-free symbol country of origin iso code abbreviation cc line 4 marking: circle = 0.75 mm diameter lower left-justified pin 1 identifier ?
si87xx 36 preliminary rev. 0.5 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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